1. Field of the Invention
The present invention relates to a sense amplifier, and more particularly to a sense amplifier for use in a non-volatile semiconductor storage device.
2. Description of the Related Art
An example of previously known sense amplifier circuits for use in a non-volatile semiconductor storage device is disclosed in the Japanese Patent Application Kokai No. Hei 2(1990)-9094, and its circuit diagram is shown in FIG. 1.
As seen from FIG. 1, the conventional sense amplifier 1 is composed of a true input circuit 11, a complementary input circuit 12, a true current mirror circuit 13, a complementary current mirror circuit 14, and an output current mirror circuit 15. Specifically, the true sense amplifier 11 which receives a true input signal SI applied through a true input terminal TI is composed of an N-channel MOS transistor (hereinafter referred to as an "NMOS" transistor) N1 and an inverter IN1, and the load therefor is the true current mirror circuit 13 consisting of P-channel MOS transistors (hereinafter referred to as "PMOS" transistors) P1 and P3. In the same manner, the complementary input circuit 12 which receives a complementary input signal SII applied through a complementary input terminal TII is composed of an NMOS transistor N2 and an inverter IN2, and the load therefor is the complementary current mirror circuit 14 consisting of PMOS transistors P2 and P4. The output current mirror circuit 15 is composed of two NMOS transistors N3 and N4 that function the loads for the current mirror circuits 13 and 14, respectively. The sense amplifier output signal SO at an output terminal TO is derived from the drain electrode of the NMOS transistor N3 in the output current mirror circuit 15.
The true and complementary input circuits 11 and 12 are symmetrical to each other. In connection with the true input circuit 11, for example, an input terminal of the inverter IN1 is connected to the source of the NMOS transistor N1, and an output terminal thereof is connected to the gate of the same NMOS transistor N1 so that a negative feedback circuit is formed thereby.
An explanation of the operation of the conventional sense amplifier 1 shown in FIG. 1 will be given hereunder.
FIG. 2 shows an arrangement of the non-volatile semiconductor storage device including a sense amplifier. The explanation on this arrangement applies also to an embodiment of the present invention which will be explained later.
As seen from FIG. 2, the non-volatile semiconductor storage device is composed of a sense amplifier 1, a column selection circuit 2, a row selection circuit 2 and a memory cell array 4.
For brevity of the following explanation, the memory cell array 4 (FIG. 2) is composed of 4 bits, i.e., two row lines W0 and W1, and two pairs of column lines D0, DI0 and D1, DI1. A pair of true and complementary memory cells, e.g., a pair of memory cells M00 and MI00 constitute 1 bit. The memory device may be an EPROM (Electrically Programmable ROM) having a plurality of FAMOSs (Floating Avalanche MOSs) as the memory cells.
In FIG. 2, each of the memory cells M00, MI01, MI10 and M11 that are not still in a programmed state turns on when the corresponding row line is selected in reading operation. On the other hand, each of the remaining memory cells MI00, M01, M10 and MI11 is already in a programmed state and its threshold voltage has been increased to about 10 V, so that even when the corresponding row line is selected, it will not turn on. Here, the pair of true and complementary input signals SI and SII in FIG. 1 correspond to a pair of true and complementary input signals at the input terminals T1 and TII in FIG. 2.
Now, on the assumption that the pair of column lines D0 and D10 are selected and fixed at this selected state wherein the pair of column lines D0 and DI0 are respectively connected, through the column selection circuit 2, to the true input terminal TI and the complementary input terminal TII of the sense amplifier, an explanation is made for the case where the selection of the row line is changed from the row line W0 to W1.
First, in the case where the row line W0 is selected whereas the W1 is not selected, the true memory cell M00 and the complementary memory cell MI00 thus selected turn "ON" and keep "OFF", respectively.
The drain current of the PMOS transistor P1 which is an input of the true current mirror circuit 13 in the sense amplifier 1 is a steady-state current which is determined by the parameter of the negative feedback circuit of the true input circuit 11 and also the characteristic or the state of the memory cell M00. Since the potential of the true input signal SI and the column line D0 is as low as about 1 V, the potential V1A at a node T1, i.e., the gate of the NMOS transistor N1, which is an output from the inverter IN1, becomes a relatively or comparatively high value.
On the contrary, since the complementary memory cell MI00 is "OFF", when the potential of the complementary input signal SII increases to the potential where the NMOS transistor N2 in the complementary input circuit 12 turns off, this NMOS transistor N2 is fixed in this state. The potential V2A at a node T2 becomes a value lower than the potential V1A appearing at the node T1. In this state, the NMOS transistor N2 is "OFF" as described above, so that the input PMOS transistor P2 of the complementary current mirror circuit 14 is also "OFF" and hence the output PMOS transistor P4 is "OFF". Thus, the NMOS transistor N4 in the output current mirror circuit 15 is "OFF" and hence the other NMOS transistor N3 therein is also "OFF".
On the other hand, the input PMOS transistor P1 of the true current mirror circuit 13 is "ON"as described previously, and hence the PMOS transistor P3 is also "ON". As a result, the potential VOA of the output signal SO at the output terminal TO becomes an "H" level which is the power supply potential.
Contrary to the above, in the case where the row line WO is not selected but the row line W1 is selected, the operation of the entire circuit proceeds in the manner entirely reverse to the explanation given above. As a result, the potential VOA of the output signal SO at the output terminal TO becomes an "L" level which is the ground potential.
For comparison to the embodiment of the present invention described later, the waveforms at the respective nodes in the conventional sense amplifier 1 described above are shown by dotted lines in FIG. 3.
The conventional sense amplifier described above has the following defect. In the steady-state, the potential difference between the gates of the NMOS transistors N1, N2 of the true and complementary input circuits 11, 12 is relatively large, so that the transition in the potential inversion at the row line selecting operation takes place at a comparatively later point in time. The transition in the conventional sense amplifier takes place at the timing point Y in FIG. 3. Thus, the sense amplifier operates at a relatively low speed.